The present invention generally relates to integrated circuits, and more particularly, to a memory error management system for an integrated circuit.
Many integrated circuits (IC) include one or more memories, such as Random Access Memory (RAM), Dynamic RAM (DRAM), and Static RAM (SRAM). The operations of the memories are controlled by a memory controller and the memories communicate with the memory controller through memory channels. Memory channels carry information, such as a corresponding channel identifier, a memory address of a corresponding memory and corresponding data/error bits. The memories are prone to errors, such as transient errors, bit flips, and the like. A memory error management system may be connected to the memory channels to identify and record the corrupted memory channel(s) using the information carried by the memory channels.
One known existing memory error management system receives the channel identifier, memory address and corresponding error bits of each memory channel and decodes memory channels containing error(s) in a current memory cycle. Thereafter, the memory error management system checks whether the decoded memory channel(s) and corresponding error(s) in the current memory cycle have already been identified and recorded in a database in previous memory cycles. When a match for a current error is present in the database, the current error is tagged as a duplicate error and the decoded information pertaining to the duplicate error is discarded. If no match is found, the current error is tagged as a unique error and the corresponding error information is stored in the database.
Thus, a lot of time and resources are used to decode memory channels that contain duplicate errors. When the memory error management system is engaged in repetitive decoding of memory channels containing duplicate or recurring errors, the decoding of memory channels containing new unique errors may either be delayed, or the new unique errors may be reported as overflows. In some applications, it is crucial not to let a unique error in the memory device go undetected and corrective action is required to be taken quickly.
Therefore, it would be advantageous to have a memory error management system that reduces decoding of corrupted memory channels corresponding to duplicate errors, that reduces the probability of overflow of unique errors, and that overcomes the above-mentioned limitations of the existing error management systems.